BiSS is an open source digital interface for sensors and actuators. BiSS is hardware compatible to the industrial standard SSI (Serial Synchronous Interface) but offers additional features and options like bidirectional data communication (serial synchronous, continuous data communication) and two unidirectional lines clock and data (cyclic at high speed (up to 10 MHz), line delay compensation for high speed data transfer, request processing times for data generation at slaves, safety capable (CRC, errors, warnings) and bus capability for multiple slaves and devices in a chain.

The advantage of open source protocols is that the selection of components  it is not imposed so the end customer can choose the proper products related to the application, increasing the cost-efficency.
Further advantage for the end customer is the compatibility between different manufactures.

 

Typical BiSS encoder connection

In point-to-point configuration, only one device with one or more slaves (sensors) is connected to the master. The master transmits the clock signal to the slave(s) via the MA line. The SL line carries the sensor data directly from the first slave back to the master. In point-to-point configuration the input SLI of the ’Last Slave’ is connected to ’0’.

In bus configuration, all devices, which may also each include multiple slaves, are connected in a chain. Each slave therefore has two terminals (SLO and SLI) with drivers provided for high speed differential signals if applicable. The MA line supplies the clock signal from the master simultaneously to all slaves and the SLO and SLI lines connect the master and all slaves in a chain.

 

Multi product BiSS connection and BiSS frame

The BiSS frame (transmission frame) is started by the master with the clock MA, clocked and ended. Here the first rising edge at MA is used for the synchronization of all slaves. It enables the isochronous scanning
of sensor data and the isochronous output of actuator data. With the 2nd rising edge from MA, all slaves set their SLO line to “0” and generate their “Ack” (Acknowledge) signal with it; it remains active (SLO = “0”) until the start bit arrives at the input SLI of the respective slave. The start bit is then passed on synchronously with the clock MA from each slave delayed by one clock pulse, while the CDS bit is either passed on by the slave or is set according to the rules of the control frame. Beginning with the 2nd bit after the start bit and up to the stop bit of the BiSS frame, the data range follows, which transmits the sensor data from the slaves to the master and the actuator data from the master to the slaves. The BiSS frame ends with the BiSS timeout. In this time no further clock pulses are sent to the MA by the master. The inverse state of the MA line during the BiSS timeout is the state of the CDM (Control Data Master) bit. At the end of the data transmission, the master sets its output MO to the idle state “1”. The
slaves then pass on this “1” received at SLI to their output SLO as soon as they have detected the expiration of the timeout themselves. This ensures that the BiSS timeout on the line SL is only signaled to the master when all connected slaves have detected the timeout.
When the BiSS timeout expires, all slaves return to the idle state; all lines are set to the high signal level (“1”) in the process.

Further infomations can be found on the BiSS website.

BiSS Encoder Eltra